This subproject is one of many research subprojects utilizing the resources provided by a Center grant funded by NIH/NCRR. Primary support for the subproject and the subproject's principal investigator may have been provided by other sources, including other NIH sources. The Total Cost listed for the subproject likely represents the estimated amount of Center infrastructure utilized by the subproject, not direct funding provided by the NCRR grant to the subproject or subproject staff. Improved fast switching of radiofrequency (r.f.) energy via PIN-diode switches is essential for receiver protection and deadtime reduction in the design of ACERT next-generation pulsed-ESR spectrometers. Fabrication of a novel, specialized electronic driver for PIN switches has previously been accomplished within the Freed Research Group (U.S. patent #5,214,315). A unique feature of this invention is that it optimizes transition speed under reactive loading conditions typical of Si and GaAs PIN-diode arrays. We are currently upgrading the driver by modeling and specifying higher-performance power MOSFET semiconductors and reformatting the switch driver as a high-performance hybrid circuit. Integration of the discrete components comprising the switch driver onto a compact ceramic substrate will significantly improve switching speed by minimizing parasitic inductance associated with the circuit interconnects. We are employing advanced commercial software tools in order to accurately model the higher-order interconnect parasitics and semiconductor characteristics;this capability allows efficient simulation and selection of newer semiconductors best-suited to this application. It also permits accurately predicting the magnitude and effect of minute parasitic reactances, greatly reducing the time required for convergence of layout variations. Simulation studies indicate that the most recent hybrid driver design should perform at the 6 - 8 ns level for charge transfers of 15-20 nC. This figure translates to probable r.f. switching speeds in the 10 - 14 ns range for high-power silicon PIN diode arrays, or 4 - 6 ns for h.v. GaAs PIN arrays. The driver hybrid assembly is physically small and can therefore be situated in close proximity to its associated PIN arrays, minimizing detrimental transmission-line effects and electromagnetic interference. We are evaluating further candidate PIN devices and plan to requisiton the hybrid drivers once the PIN diodes have been characterized in the context of our ongoing microwave spectrometer development.